This application claims the priority benefit of Taiwan application serial no. 89124635, filed Nov. 21, 2000.
1. Field of Invention
The present invention relates to a clock circuit structure for a motherboard. More particularly, the present invention relates to a clock circuit structure for the motherboard of a personal computer capable of supporting two or more memory module types.
2. Description of Related Art
In general, a personal computer system consists of a motherboard, some interface cards, and a number of peripheral devices. The motherboard is often considered as the core of a computer system. Besides a central processing unit (CPU), a chipset, and various slots for connecting a variety of interface cards, the motherboard further includes a plurality of memory module slots for connecting memory modules. Different number of memory modules may be connected into the slots depending on actual requirements of the user. Each memory module includes a plurality of memory devices assembled together into a package.
At present, the most commonly used memory modules include the synchronous dynamic random access memory (SDRAM). SDRAM operates in response to the rising edge of a system clock signal. Hence, the SDRAM only uses the rising edge to initiate subsequent data access, and control operations. Following the rapid progress in semiconductor fabricating technologies, a double data rate (DDR) SDRAM has been developed. As the name implies, the DDR dynamic random access memory (DRAM) has a data access rate twice that of the SDRAM. The DDR memory can achieve this because it is triggered at both the rising edge and the falling edge of a system clock signal. Hence, DDR DRAM is able to perform two transactions within a single clock
Major differences between synchronous dynamic random access memory (SDRAM), and double data rate (DDR) DRAM includes the following: (1) SDRAM uses ordinary clock pulse signal while DDR DRAM uses a differential clock signal; (2) SDRAM uses a voltage VDD=3.3V while DDR DRAM uses a voltage VDD=2.5V and VDDQ=2.5V; (3) SDRAM requires no reference voltage while DDR DRAM do need a reference voltage of xc2xd VDDQ; (4) the data bus that connects with the SDRAM is generally CMOS logic while the data bus that connects with the DDR DRAM is series stub terminated logic 2 (SSTL_2); (5) SRAM data bus requires no terminated voltage (VTT) while DDR DRAM data bus needs to have a terminated voltage (VTT) for absorbing reflected electromagnetic wave; and (6) SDRAM bus requires no pull-up resistor while DDR DRAM bus needs a pull-up resistor.
Due to the aforementioned differences, most motherboards on the market can support either one of the memory modules. A motherboard that supports DDR DRAM modules uses a 184-pin slot design according to JEDEC specification. On the other hand, a motherboard that supports SDRAM uses a 168-pin memory module slot. This is because the signal leads of 184-pin and 168-pin slots are totally different. If a motherboard is designed to fit the layout of a 184-pin slot, considerations such as motherboard size and signal attenuation renders the fitting of a 168-pin slot on the same motherboard difficult. The same difficulties occur for fitting a 184-pin slot onto a motherboard originally designed to accommodate a 168-pin slot.
At present, due to mass production, a great number of SDRAM modules are produced, and available in the market. The stock of SDRAM modules is plentiful and the cost is cheaper. A user looking for a computer system may buy a computer system with SDRAM memory modules because of this price consideration. If price of DDR DRAM is subsequently lowered, the slower SDRAM may want to be replaced instead of having to replace the motherboard or purchase a new computer system. On the other hand, a retailer or manufacturer of motherboard may want a motherboard that supports both the 184-pin DDR DRAM as well as the 168-pin SDRAM to lower production costs, and stocking risk.
In the meantime, a clock buffer that can support both types of memories are absent from the market currently. To design a motherboard capable of supporting 184-pin DDR DRAM modules, and 168-pin SDRAM modules at the same time, two different clock buffers have to be installed. Hence, size of the motherboard will likely increase. Conversely, if a constant size needs to be maintained, layout design of the motherboard is rendered difficult. Furthermore, using two separate clock buffers is likely to produce more electromagnetic radiation than a single clock buffer.
Accordingly, one object of the present invention is to provide a clock circuit and an associated clock buffer capable of supporting a plurality of memory modules. Only a single clock buffer is used to drive the plurality of different memory modules so that difficulties in designing a motherboard layout is reduced, while a constant motherboard size is maintained, and less electromagnetic radiation is produced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a clock circuit for supporting a plurality of memory module types. The clock circuit is connected to a first type memory module slot, and a second type memory module slot. The first type memory module slot has a first type memory clock pin for receiving a first type memory clock signal. The second type memory module slot has a second type memory clock pin for receiving a second type memory clock signal. The clock circuit includes a clock generator for producing a clock signal, and a clock buffer that connects to all of the aforementioned devices. The clock buffer has doubly defined clock pins capable of outputting the first type memory clock signal or the second type memory clock signal. The clock buffer receives the clock signal and outputs a first type memory clock signal to the first type memory clock pin. The doubly defined clock pin outputs a second type memory clock signal to the second type memory clock pin.
The clock circuit for supporting a plurality of memory module types further includes a control chipset connected to the clock buffer. The control chipset controls the clock buffer so that either the first type memory clock signal or the second type memory clock signal are outputted. The clock buffer further includes an inverse tri-state buffer and a tri-state buffer. The tri-state buffer has an input terminal connected to a clock signal terminal, and an output terminal connected to the doubly defined clock pin. The tri-state buffer has an input terminal connected to a clock signal terminal and an output terminal connected to the doubly defined clock pin. When the doubly defined clock pin outputs a first type memory clock signal, the inverse tri-state buffer produces an output while the output of the tri-state buffer is at a high impedance state. Conversely, when the doubly defined clock pin outputs a second type memory clock signal, the tri-state buffer produces an output while the output of the inverse tri-state buffer is at a high impedance state.
In this invention, a tri-state buffer, and an inverse tri-state buffer are produced on the same piece of silicon chip, and control of the silicon chip is selected by inputting control signals. Consequently, a clock buffer and a clock circuit for supporting different memory module types is produced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.